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8XC196KC/8XC196KC20 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
87C196KC-16 Kbytes of On-Chip OTPROM 83C196KC-16 Kbytes ROM 80C196KC-ROMless Y Dynamically Configurable 8-Bit or 16 and 20 MHz Available 16-Bit Buswidth 488 Byte Register RAM Register-to-Register Architecture
Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y
Full Duplex Serial Port High Speed I/O Subsystem 16-Bit Timer 16-Bit Up/Down Counter with Capture 3 Pulse-Width-Modulated Outputs Four 16-Bit Software Timers 8- or 10-Bit A/D Converter with Sample/Hold HOLD/HLDA Bus Protocol OTPROM One-Time Programmable Version
28 Interrupt Sources/16 Vectors Peripheral Transaction Server 1.4 ms 16 x 16 Multiply (20 MHz) 2.4 ms 32/16 Divide (20 MHz) Powerdown and Idle Modes Five 8-Bit I/O Ports 16-Bit Watchdog Timer Extended Temperature Available
Y Y
The 80C196KC 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family. The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an optional 16 Kbytes of ROM/OTPR OM. Intel's CHMOS III process provides a high performance processor along with low power consumption. The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16 Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise stated. Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform generation. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or up/down counter. With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of 0 C to a 70 C. With the extended (Express) temperature range option, operational characteristics are guaranteed over the temperature range of b 40 C to a 85 C. Unless otherwise noted, the specifications are the same for both options. See the Packaging information for extended temperature designators.
Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT (c) INTELCORPORATION,2004 Order Number:270942-006 July 2004
8XC196KC/8XC196KC20
270942 1
Figure 1. 8XC196KC Block Diagram IOC3 (0CH HWIN1 READ/WRITE)
270942 45
NOTE: RSV-Reserved bits must be e
0
Figure 2. 8XC196KC New SFR Bit (CLKOUT Disable)
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8XC196KC/8XC196KC20
PROCESS INFORMATION
This device is manufactured on PX29.5 or PX29.9, a CHMOS III process. Additional process and reliability information is available in the Intel(R) Quality System Handbook: http://developer.intel.com/design/quality/quality.htm
Table 2. 8XC196KC Memory Map Description External Memory or I/O Internal ROM/OTPROM or External Memory (Determined by EA) Reserved. Must contain FFH. (Note 5) PTS Vectors Upper Interrupt Vectors ROM/OTPROM Security Key Reserved. Must contain FFH. (Note 5)
270942 - 43
Address 0FFFFH 06000H 5FFFH 2080H 207FH 205EH 205DH 2040H 203FH 2030H 202FH 2020H 201FH 201AH 2019H 2018H 2017H 2014H 2013H 2000H 1FFFH 1FFEH 1FFDH 0200H 01FFH 0018H 0017H 0000H
Reserved. Must Contain 20H. (Note 5) CCB Reserved. Must contain FFH. (Note 5) Lower Interrupt Vectors Port 3 and Port 4
NOTE: 1. EPROMs are available as One Time Programmable (OTPROM) only.
Figure 3. The 8XC196KC Family Nomenclature Table 1. Thermal Characteristics Package Type PLCC QFP SQFP ja 35C/W 55C/W TBD jc 13 C/W 16 C/W TBD
External Memory 488 Bytes Register RAM (Note 1) CPU SFR's (Notes 1, 3, 4)
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology.
NOTES: 1. Code executed in locations 0000H to 01FFH will be forced external. 2. Reserved memory locations must contain 0FFH unless noted. 3. Reserved SFR bit locations must contain 0. 4. Refer to 8XC196KC User's manual for SFR descriptions. 5. WARNING: Reserved memory locations must not be written or read. The contents and/or function of these locations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly.
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8XC196KC/8XC196KC20
270942 - 2
Figure 4. 68-Lead PLCC Package
4
8XC196KC/8XC196KC20
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Figure 5. 8XC196KC 80-Pin QFP Package
5
8XC196KC/8XC196KC20
270942 - 44
Figure 6. 80-Pin SQFP Package
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8XC196KC/8XC196KC20
PIN DESCRIPTIONS
Symbol VCC VSS VREF ANGND VPP XTAL1 XTAL2 CLKOUT RESET BUSWIDTH NMI INST EA Name and Function Main supply voltage (5V). Digital circuit ground (0V). There are multiple VSS pins, all of which must be connected. Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. Timing pin for the return from powerdown circuit. This pin also supplies the programming voltage on the EPROM device. Input of the oscillator inverter and of the internal clock generator. Output of the oscillator inverter. Output of the internal clock generator. The frequency of CLKOUT is frequency. the oscillator
Reset input and open drain output. Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. A positive transition causes a vector through 203EH. Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. Input for memory select (External Access). EA equal high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip ROM/E PROM. EA equal to low causes accesses to those locations to be directed to off-chip memory. Also used to enter programming mode. Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. Read signal output to external memory. RD is activated only during external memory reads. Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes. Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit. 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. 8-bit quasi-bidirectional I/O port. 8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC. Pins 2.6 and 2.7 are quasi-bidirectional.
ALE/ADV
RD WR/WRL BHE/WRH
READY HSI HSO Port 0 Port 1 Port 2
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8XC196KC/8XC196KC20
PIN DESCRIPTIONS (Continued)
Symbol Ports 3 and 4 HOLD HLDA BREQ PMODE PACT CPVER PALE PROG PVER AINC Name and Function 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. Bus Hold input requesting control of the bus. Bus Hold acknowledge output indicating release of the bus. Bus Request output activated when the bus controller has a pending external memory cycle. Determines the EPROM programming mode. A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete. Cummulative Program Output Verification. Pin is high if all locations have programmed correctly since entering a programming mode. A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid programming data (input to slave). A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. Auto Increment. Active low input signal indicates that the auto increment mode is enabled. Auto Increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write.
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8XC196KC/8XC196KC20
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias.....................................-55 to +125C Storage Temperature.........................-65 to +150C Voltage On Any Pin to VSS.................-0.5V to +7.0V(1) Voltage from EA or VPP to VSS or ANGND..............................+13.00V
NOTICE: This is a production data sheet. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice.
WARNING: Stressing the device beyond the Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions'' is not recommended and extended exposure beyond the Operating Conditions'' may affect device reliability.
Power Dissipation...........................................1.5W(2)
NOTE: 1. This includes VPP and EA on ROM or CPU only devices. 2. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
Symbol TA TA VCC VREF ANGND FOSC FOSC Description Ambient Temperature Under Bias Commercial Temp. Ambient Temperature Under Bias Extended Temp. Digital Supply Voltage Analog Supply Voltage Analog Ground Voltage Oscillator Frequency (8XC196KC) Oscillator Frequency (8XC196KC20) Min 0
b 40
Max
a 70 a 85
Units C C V V V(1) MHz MHz
4.50 4.00 VSS b 0.4 8 8
5.50 5.50 VSS a 0.4 16 20
NOTE: 1. ANGND and VSS should be nominally at the same potential.
DC CHARACTERISTICS
Symbol VIL VIH VIH1 VIH2 VHYS VOL Description Input Low Voltage
(Over Specified Operating Conditions) Min
b 0.5
Typ
Max 0.8 VCC a 0.5 VCC a 0.5 VCC a 0.5 0.3 0.45 1.5 0.8
Units V V V V mV V V V V V V V
TestConditions
Input High Voltage (Note 1) Input High Voltage on XTAL 1 Input High Voltage on RESET Hysteresis on RESET Output Low Voltage
0.2 VCC a 1.0 0.7 VCC 2.2 300
VCC e 5.0V IOL e 200 mA IOL e 2.8 mA IOL e 7 mA IOL e a 0.4 mA IOH e b 200 mA IOH e b 3.2 mA IOH e b 7 mA
VOL1 VOH
Output Low Voltage in RESET on P2.5 (Note 2) Output High Voltage (Standard Outputs) VCC b 0.3 VCC b 0.7 VCC b 1.5
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8XC196KC/8XC196KC20
DC CHARACTERISTICS
Symbol Description VOH1
(Over Specified Operating Conditions) (Continued) Min VCC b 0.3 VCC b 0.7 VCC b 1.5
b 0.8
Typ Max
Units TestConditions V V V mA IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA VIH e VCC b 1.5V
Output High Voltage (Quasi-bidirectional Outputs) Logical 1 Output Current in Reset. on P2.0. Do not exceed this or device may enter test modes. Logical 0 Input Current in Reset on P2.0. Maximum current that must be sunk by external device to ensure test mode entry. Logical 1 Input Current. Maximum current that external device must source to initiate NMI. Input Leakage Current (Std. Inputs) Input Leakage Current (Port 0) 1 to 0 Transition Current (QBD Pins) Logical 0 Input Current (QBD Pins) Ports 3 and 4 in Reset Active Mode Current in Reset (8XC196KC) Active Mode Current in Reset (8XC196KC20) Idle Mode Current (8XC196KC) Idle Mode Current (8XC196KC20) Powerdown Mode Current A/D Converter Reference Current Reset Pullup Resistor Pin Capacitance (Any Pin to VSS)
IOH1
IIL2
TBD
mA
VIN e 0.45V
IIH1
a 200
mA
VIN e VCC e 2.4V
ILI ILI1 ITL IIL IIL1 ICC ICC IIDLE IIDLE IPD IREF RRST CS
g10 g3
mA mA mA mA mA mA mA mA mA mA mA X pF
0 k VIN k VCC b 0.3V 0 k VIN k VREF VIN e 2.0V VIN e 0.45V VIN e 0.45V XTAL1 e 16 MHz VCC e VPP e VREF e 5.5V XTAL1 e 20 MHz VCC e VPP e VREF e 5.5V XTAL1 e 16 MHz VCC e VPP e VREF e 5.5V XTAL1 e 20 MHz VCC e VPP e VREF e 5.5V VCC e VPP e VREF e 5.5V VCC e VPP e VREF e 5.5V VCC e 5.5V, VIN e 4.0V
b 650 b 70 b 70
65 80 17 21 8 2 6K
75 92 25 30 15 5 65K 10
NOTES: 1. All pins except RESET and XTAL1. 2. Violating these specifications in Reset may cause the part to enter test modes. 3. Commercial specifications apply to express parts except where noted. 4. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. 5. Standard Outputs include AD015, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4, TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs. 6. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4. 7. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held below VCC b 0.7V: IOL on Output pins: 10 mA IOH on quasi-bidirectional pins: self limiting IOH on Standard Output pins: 10 mA 8. Maximum current per bus pin (data and control) during normal operation is g3.2 mA. 9. During normal (non-transient) conditions the following total current limits apply: IOH is self limiting Port 1, P2.6 IOL: 29 mA IOH: 26 mA HSO, P2.0, RXD, RESET IOL: 29 mA IOL: 13 mA IOH: 11 mA P2.5, P2.7, WR, BHE IOH: 52 mA AD0AD15 IOL: 52 mA IOH: 13 mA RD, ALE, INSTCLKOUT IOL: 13 mA
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8XC196KC/8XC196KC20
ICC Max e 4.13 c Frequency a 9 mA ICC Typ e 3.50 c Frequency a 9 mA IIDLE Max e 1.25 c Frequency a 5 mA IIDLE Typ e 0.88 c Frequency a 3 mA NOTE: Frequencies below 8 MHz are shown for reference only; no testing is performed.
270942 17
Figure 7. I CC and I IDLE vs Frequency
AC CHARACTERISTICS
For use over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz The system must meet these specifications Symbol TAVYV TYLYH TCLYX TLLYX TAVGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRXDX Description Address Valid to READY Setup Non READY Time READY Hold after CLKOUT Low READY Hold after ALE Low Address Valid to Buswidth Setup Buswidth Hold after CLKOUT Low Address Valid to Input Data Valid RD Active to Input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD Inactive 0 0 3 TOSC b 55 TOSC b 22 TOSC b 45 TOSC 0 TOSC b 15 to work with the 80C196KC: Min Max 2 TOSC b 68 No upper limit TOSC b 30 2 TOSC b 40 2 TOSC b 68 Units ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 2) (Note 1) (Note 1) Notes
NOTES: 1. If max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC N, where N e number of wait states.
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8XC196KC/8XC196KC20
AC CHARACTERISTICS
(Continued) For user over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz
The 80C196KC will meet these specifications: Symbol FXTAL FXTAL TOSC TOSC TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Description Frequency on XTAL1 (8XC196KC) Frequency on XTAL1 (8XC196KC20) I/F XTAL (8XC196KC) I/F XTAL (8XC196KC20) XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling Edge to ALE Rising ALE Falling Edge to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Falling Edge Address Hold after ALE Falling Edge ALE Falling Edge to RD Falling Edge RD Low to CLKOUT Falling Edge RD Low Period RD Rising Edge to ALE Rising Edge RD Low to Address Float ALE Falling Edge to WR Falling Edge CLKOUT Low to WR Falling Edge Data Stable to WR Rising Edge CLKOUT High to WR Rising Edge WR Low Period Data Hold after WR Rising Edge WR Rising Edge to ALE Rising Edge BHE, INST after WR Rising Edge AD815 HOLD after WR Rising BHE, INST after RD Rising Edge AD815 HOLD after RD Rising TOSC b 10 0 TOSC b 23
b5 a 15 a 25 b5 b 20
Min 8 8 62.5 50
a 20
Max 16 20 125 125
a 110
Units MHz MHz ns ns ns ns ns ns ns ns
Notes (Note 1) (Note 1)
2 TOSC TOSC b 10 TOSCa 15
a 15 a 15
4 TOSC TOSC b 10 TOSC b 15 TOSC b 35 TOSC b 30
a4 a 30
(Note 4)
TOSCa 10
ns ns ns ns ns (Note 4) (Note 2) ns ns ns ns (Note 4) ns ns ns (Note 4) (Note 2) (Note 3) (Note 3)
TOSC b 5 TOSC TOSC a 25
a5
TOSC b 20 TOSC b 25 TOSC b 10 TOSC b 10 TOSC b 30 TOSC b 10 TOSC b 25 TOSC a 15
ns ns ns ns ns
NOTES: 1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 2. Assuming back-to-back bus cycles. 3. 8-Bit bus only. 4. If wait states are used, add 2 TOSC N, where N e number of wait states.
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8XC196KC/8XC196KC20
System Bus Timings
270942 18
13
8XC196KC/8XC196KC20
READY Timings (One Wait State)
270942 20
Buswidth Timings
270942 35
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8XC196KC/8XC196KC20
HOLD/HLDA Timings
Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV TCLLH HOLD Setup CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE, INST, RD, WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE, INST, RD, WR Valid CLKOUT Low to ALE High
b 15 b 15 b 15 b 10 b5 a 15 a 15
Description
Min
a 55 b 15 b 15
Max
a 15 a 15 a 15 a 20 a 15 a 15
Units ns ns ns ns ns ns ns ns ns ns
Notes (Note 1)
NOTE: 1. To guarantee recognition at next clock.
DC SPECIFICATIONS IN HOLD Description Weak Pullups on ADV, RD, WR, WRL, BHE Weak Pulldowns on ALE, INST Min 50K 10K Max 250K 50K Units VCC e 5.5V, VIN e 0.45V VCC e 5.5V, VIN e 2.4
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8XC196KC/8XC196KC20
270942 36
Maximum Hold Latency Bus Cycle Type Internal Execution 16-Bit External Execution 8-Bit External Execution 1.5 States 2.5 States 4.5 States
EXTERNAL CLOCK DRIVE (8XC196KC)
Symbol 1/T XLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period High Time Low Time Rise Time Fall Time Min 8 62.5 20 20 10 10 Max 16.0 125 Units MHz ns ns ns ns ns
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8XC196KC/8XC196KC20
EXTERNAL CLOCK DRIVE (8XC196KC20)
Symbol 1/T XLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period High Time Low Time Rise Time Fall Time Min 8 50 17 17 8 8 Max 20.0 125 Units MHz ns ns ns ns ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270942 21
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
270942 41
270942 42
NOTE: Keep oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and VSS. When 20 pF. When using ceramic using crystals, C1 e C2 resonators, consult manufacturer for recommended circuitry.
NOTE: Required if TTL driver used. Not needed if CMOS driver is used.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270942 22 AC Testing inputs are driven at 2.4V for a Logic 1'' and 0.45V for a Logic 0'' Timing measurements are made at 2.0V for a Logic 1'' and 0.8V for a Logic 0''.
270942 23 For Timing Purposes a Port Pin is no Longer Floating when a 150 mV change from Load Voltage Occurs and Begins to Float when a 150 mV change from the Loaded VOH/V OL Level occurs; IOL/I OH e g15 mA.
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8XC196KC/8XC196KC20
EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by T'' for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: HLVXZHigh Low Valid No Longer Valid Floating Signals: ABCDGHAddress BHE CLKOUT DATA Buswidth HOLD LALE/ADV BR- BREQ RWXYQRD WR/WRH /WRL XTAL1 READY Data Out
HA- HLDA
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE 0) Symbol TXLXL TXLXH TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ Parameter Serial Port Clock Period (BRR t 8002H) Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) Serial Port Clock Period (BRR e 8001H) Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float TOSC a 50 0 1 TOSC Min 6 TOSC 4 TOSC b 50 4 TOSC 2 TOSC b 50 2 TOSC b 50 2 TOSC b 50 2 TOSC a 50 2 TOSC a 50 4 TOSC a 50 Max Units ns ns ns ns ns ns ns ns ns ns
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE (MODE 0)
270942 24
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8XC196KC/8XC196KC20
A to D CHARACTERISTICS
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF.
10-BIT MODE A/D OPERATING CONDITIONS
Symbol TA TA VCC VREF TSAM TCONV FOSC FOSC Description Ambient Temperature Commercial Temp. Ambient Temperature Extended Temp. Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency (8XC196KC) Oscillator Frequency (8XC196KC20) Min 0
b 40
Max
a 70 a 85
Units C C V V ms(1) ms(1) MHz MHz
4.50 4.00 1.0 10 8.0 8.0
5.50 5.50 20 16.0 20.0
NOTE: ANGND and VSS should nominally be at the same potential, 0.00V. 1. The value of AD_TIME is selected to meet these specifications.
10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Error Channel-to-Channel Matching Repeatability Temperature Coefficients: Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin DC Input Leakage Sampling Capacitor 3
b 60 b 60
g0.1 g0.25
Typical (1)
Minimum 1024 10 0
Maximum 1024 10
g3
Units Levels Bits LSBs LSBs LSBs
*Notes
0.25 g 0.5 0.25 g 0.5 1.0 g 2.0 0
lb 1 g3
LSBs LSBs LSBs LSBs LSB/ C LSB/ C LSB/ C
a2
g1
0
0.009 0.009 0.009
b 60
dB dB dB
1, 2 1 1 4 5, 6
750 ANGND b 0.5 0
1.2K VREF a 0.5
g3.0
X V mA pF
NOTES: An LSB'' as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25 C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted. 7. All conversions performed with processor in IDLE mode.
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8XC196KC/8XC196KC20
8-BIT MODE A/D OPERATING CONDITIONS
Symbol TA TA VCC VREF TSAM TCONV FOSC FOSC Description Ambient Temperature Commercial Temp. Ambient Temperature Extended Temp. Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency (8XC196KC) Oscillator Frequency (8XC196KC20) Min 0
b 40
Max
a 70 a 85
Units C C V V ms(1) ms(1) MHz MHz
4.50 4.00 1.0 7 8.0 8.0
5.50 5.50 20 16.0 20.0
NOTE: ANGND and VSS should nominally be at the same potential, 0.00V. 1. The value of AD_TIME is selected to meet these specifications.
8-BIT MODE A/D CHARACTERISTICS
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Error Channel-to-Channel Matching Repeatability Temperature Coefficients: Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin DC Input Leakage Sampling Capacitor 3
b 60 b 60
g0.25 g0.5 g0.5
(Over Specified Operating Conditions) Minimum 256 8 0 Maximum 256 8
g1
Typical
Units Levels Bits LSBs LSBs LSBs
Notes
0
lb 1
g1
LSBs LSBs LSBs LSBs LSB/ C LSB/ C LSB/ C
a1
g1
0.003 0.003 0.003
b 60
dB dB dB
2, 3 2 2 4 5, 6
750 VSS b 0.5 0
1.2K VREF a 0.5
g3.0
Xs V mA pF
NOTES: An LSB'' as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25 C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted. 7. All conversions performed with processor in IDLE mode.
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8XC196KC/8XC196KC20
EPROM SPECIFICATIONS OPERATING CONDITIONS DURING PROGRAMMING
Symbol TA VCC VREF VPP VEA FOSC FOSC FOSC Description Ambient Temperature During Programming Supply Voltage During Programming Reference Supply Voltage During Programming Programming Voltage EA Pin Voltage Oscillator Frequency During Auto and Slave Mode Programming Oscillator Frequency During Run-Time Programming (8XC196KC) Oscillator Frequency During Run-Time Programming (8XC196KC20) Min 20 4.5 4.5 12.25 12.25 6.0 6.0 6.0 Max 30 5.5 5.5 12.75 12.75 8.0 16.0 20.0 Units C V(1) V(1) V(2) V(2) MHz MHz MHz
NOTES: 1. VCC and VREF should nominally be at the same voltage during programming. 2. VPP and VEA must never exceed the maximum specification, or the device may be damaged. 3. VSS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol TSHLL TLLLH TAVLL TLLAX TPLDV TPHDX TDVPL TPLDX TPLPH(1) TPHLL TLHPL TPHPL TPHIL TILIH TILVH TILPL TPHVL Description Reset High to First PALE Low PALE Pulse Width Address Setup Time Address Hold Time PROG Low to Word Dump Valid Word Dump Data Hold Data Setup Time Data Hold Time PROG Pulse Width PROG High to Next PALE Low PALE High to PROG Low PROG High to Next PROG Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Valid 0 400 50 220 220 220 0 240 50 170 220 Min 1100 50 0 100 50 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC
NOTE: 1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. See user's manual for further information.
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8XC196KC/8XC196KC20
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol IPP Description VPP Supply Current (When Programming) Min Max 100 Units mA
NOTE: Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270942 27
NOTE: P3.0 must be high (1'')
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
270942 28
NOTE: P3.0 must be low (0'')
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8XC196KC/8XC196KC20
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT
270942 29
8XC196KB TO 8XC196KC DESIGN CONSIDERATIONS
1. Memory Map. The 8XC196KC has 512 bytes of RAM/SFRs and an optional 16K of ROM/OTPR OM. The extra 256 bytes of RAM will reside in locations 100H 1FFH and the extra 8K of ROM/OTPR OM will reside in locations 4000H 5FFFH. These locations are external memory on the 8XC196KB. 2. The CDE pin on the KB has become a VSS pin on the KC to support 16/20 MHz operation. 3. EPROM programming. The 8XC196KC has a different programming algorithm to support 16K of on-board memory. When performing Run-Time Programming, use the section of code in the 8XC196KC User's Guide.
4. ONCE Mode Entry. The ONCE mode is entered on the 8XC196KC by driving the TXD pin low on the rising edge of RESET. The TXD pin is held high by a pullup that is specified by IOH1. This Pullup must not be overridden or the 8XC196KC will enter the ONCE mode. 5. During the bus HOLD state, the 8XC196KC weakly holds RD, WR, ALE, BHE and INST in their inactive states. The 8XC196KB only holds ALE in its inactive state. 6. A RESET pulse from the 8XC196KC is 16 states rather than 4 states as on the 8XC196KB (i.e., a watchdog timer overflow). This provides a longer RESET pulse for other devices in the system.
8XC196KC ERRATA
1. Missed EXTINT on P0.7. The 80C196KC20 could possibly miss an EXTINT on P0.7. See techbit MC0893. 2. HSI_MODEdivide-by-eight. See Faxback 2192. 3. IPD hump. See Faxback 2311.
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8XC196KC/8XC196KC20
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a H'', L'' or M'' at the end of the topside tracking number. The topside tracking number consists of nine characters and is the second line on the top side of the device. Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. The following are differences between the 270942-006 datasheet and the 270942-005 datasheet: 1. Package prefix variables have changed. Variables are now indicated by an "x" The following are differences between the 270942-004 and 270942-005 datasheets: 1. Removed Word Addressable Only'' from Port 3 and 4 in Table 2. 2. Renamed PVAL to CPVER. 3. Removed TLLYV and TLLGV from the waveform diagrams. 4. Added HSI_MODE divide-by-eight and IPD hump to 8XC196KC errata. The following are important differences between the 270942-002 and 270942-004 data sheets: 1. NMI during PTS, QBD port glitch and Divide HOLD/READY erratas were fixed and have been removed from the data sheet. The HSI errata is also removed as this is now considered normal operation. 2. Combined 16 and 20 MHz data sheets. Data sheet 270924-001 (20 MHz) is now obsolete. 3. Added 80-lead SQFP package pinout. 4. Added documentation for CLKOUT disable bit. 5. iJA for QFP package was changed to 55 C/W from 42 C/W. 6. iJC for QFP package was changed to 16 C/W from TBD C/W. 7. TSAM (MIN) in 10-bit mode was changed to 1.0 ms from 3.0 ms. 8. TSAM (MIN) in 8-bit mode was changed to 1.0 ms from 2.0 ms. 9. IIL1 specification for port 2.0 was renamed IIL2. 10. IIL2 (MAX) is changed to TBD from b 6 mA. IIH1 (MAX) is changed to a 200 mA from a 100 mA. IIH1 test condition changes to VIN e 2.4V from VIN e 5.5V. 13. VHYS is changed to 300 mV from 150 mV. 14. ICC (TYP) at 16 MHz is changed to 65 mA from 50 mA. 11. 12. 15. 16. 18. 19. ICC (MAX) at 16 MHz is changed to 75 mA from 70 mA. ICC (TYP) at 20 MHz is changed to 80 mA from 60 mA.
17. ICC (MAX) at 20 MHz is changed to 92 mA from 86 mA. IIDLE (TYP) at 16 MHz is changed to 17 mA from 15 mA. IIDLE (MAX) at 16 MHz is changed to 25 mA from 30 mA. 20. IIDLE (TYP) at 20 MHz is changed to 21 mA from 15 mA. 21. IIDLE (MAX) at 20 MHz is changed to 30 mA from 35 mA. 22. IPD (TYP) at 16 MHz is changed to 8 mA from 15 mA. 23. IPD (MAX) at 16 MHz is changed to 15 mA from TBD. 24. IPD (TYP) at 20 MHz is changed to 8 mA from 18 mA. 25. IPD (MAX) at 20 MHz is changed to 15 mA from TBD. 26. TCLDV (MAX) is changed to TOSC b 45 ns from TOSC b 50 ns. 27. TLLAX (MIN) is changed to TOSC b 35 ns from TOSC b 40 ns. 28. TCHWH (MIN) is changed to b 5 ns from b 10 ns. 29. TRHAX (MIN) is changed to TOSC b 25 ns from TOSC b 30 ns. 30. THALAZ (MAX) is changed to a 15 ns from a 10 ns. 31. THALBZ (MAX) is changed to a 20 ns from a 15 ns.
8XC196KC/8XC196KC20
32. THAHBV (MAX) is now specified at a 15 ns, was formerly unspecified. 33. The TLLYV and TLLGV specifications were removed. These specifications are not required in high-speed systems designs. 34. Added EXTINT, P0.7 errata to Errata section. The following are the important differences between the -001 and -002 versions of data sheet 270942. 1. Express and Commercial devices are combined into one data sheet. The Express only data sheet 270794-001 is obsolete. 2. Removed KB/KC feature set differences, pin definition table, and SFR locations and bitmaps. 3. Added programming pin function to package drawings and pin descriptions. 4. Changed absolute maximum temperature under bias from 0 C to a 70 C to b 55 C to a 125 C. 5. Replaced VOH2 specification with IOH1 and IIL1 specifications. 6. Added IIH1 specification for NMI pulldown resistors. 7. Added maximum hold latency table. 8. Added external oscillator and external clock circuit drawings. 9. Changed Clock Drive TXHXX and TXLXX Min spec to 20 ns. 10. Fixed Serial Port TXLXH specification. 11. Added 8- and 10-bit mode A/D operating conditions tables. 12. Specified operating range for sample and convert times. 13. Added specification for voltage on analog input pin. 14. Put operating conditions for EPROM programming into tabular format.
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